DDR Configuration Report
General Information
DDR Type : LPDDR4 FLASH
Firmware version : 2021_05_T_129754
UI Configuration
Device Information :
-
Clock Cycle Freq (MHz) : 800 Mhz
-
XOSC clock frequency (MHz) : 40 MHz
-
FM Center Spread Enabled : Disabled
-
Chip Select Information :
-
Starting Address for CS0 (HEX) : 0x80000000
-
Size of CS0 (MB) : 32
-
Starting Address for CS1 (HEX) : 0x0
-
Size of CS1 (MB) : 0
-
Rank interleaving : Disabled
-
ECC options :
-
Enable ECC : Enabled
-
Note : Enabling ECC provides SEC/DED functionality - single bit error correction and double bit error detection.
-
Error Handling :
-
Enable Interrupts : Disabled
-
Initial Board Settings :
-
PHY ODT Impedance : 60 Ohm
-
PHY Vref Quotient : 0x14
-
PHY Vref : 0.172 V
-
DRAM Drive Strength : 40 Ohm
-
Train 2D : Disabled
-
PHY Log Level : Firmware complete
-
DQ Swapping :
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Code Generation :
-
Code format : U-boot
-
Debug :
-
Save debug messages : Disabled
Mode Registers
| # |
value |
OP [7] |
OP [6] |
OP [5] |
OP [4] |
OP [3] |
OP [2] |
OP [1] |
OP [0] |
| MR1 | 0x00 | RPST = 0x0 | nWR = 0x0 | RD-PRE = 0x0 | WR-PRE = 0x0 | BL = 0x0 |
| MR2 | 0x02 | WR Lev = 0x0 | WLS = 0x0 | WL = 0x0 | RL = 0x2 |
| MR3 | 0x71 | DBI-WR = 0x0 | DBI-RD = 0x1 | PDDS = 0x6 | PPRP = 0x0 | WR PST = 0x0 | PU-CAL = 0x1 |
| MR4 | 0x00 | TUF = 0x0 | Thermal Offset = 0x0 | PPRE = 0x0 | SR Abort = 0x0 | Refresh Rate = 0x0 |
| MR11 | 0x60 | Reserved = 0x0 | CA ODT = 0x6 | Reserved = 0x0 | DQ ODT = 0x0 |
| MR12 | 0x4D | CBT Mode = 0x0 | VR-CA = 0x1 | Vref CA = 0xd |
| MR13 | 0x08 | FSP-OP = 0x0 | FSP-WR = 0x0 | DMD = 0x0 | RRO = 0x0 | VRCG = 0x1 | VRO = 0x0 | RPT = 0x0 | CBT = 0x0 |
| MR14 | 0x00 | RFU = 0x0 | VR DQ = 0x0 | VREF DQ = 0x0 |
| MR16 | 0x00 | PASR Bank Mask = 0x0 |
| MR17 | 0x00 | PASR Segment Mask = 0x0 |
| MR22 | 0x04 | ODTD x8 Mode = 0x0 | ODTD-CA = 0x0 | ODTE-CS = 0x0 | ODTE-CK = 0x0 | SOC ODT = 0x4 |
| MR24 | 0x00 | TRR Mode = 0x0 | TRR Mode BAn = 0x0 | Unlimited = 0x0 | MAC Value = 0x0 |